With the continuous development of intelligent wearable technologies, more and more wearable apparatus have penetrated into every part of people's daily life. The intelligent wearable apparatus includes intelligent watches, and heath wristbands, etc. For the development of the wearable apparatus, the size and the power consumption are the two key factors to evaluate if a wearable apparatus is able to attract customers' attentions. For the intensively competitive market of the wearable apparatus, weather the wearable apparatus are able to attract the customers' attentions determines the success of the wearable apparatus in the market. Therefore, almost all of the manufacturers of the wearable apparatus focus on the size and the power consumption of the wearable apparatus when the wearable devices are developed.
Considering the size and the power consumption of the wearable apparatus, as one of the important type of components in the wearable devices, static random access memory (SRAM) needs to meet the requirements of high performance, low power-consumption and small size. The current approach to reduce the power consumption of the SRAM is to use a retention mode to reduce the supply voltage of the SRAM. Under such a supply voltage, the memory cells of the SRAM are only able to store data; and such a supply voltage is referred to as a data retention voltage (DRV).
In a low-power SRAM design, the retention mode is often achieved by a double-source voltage structure. When the circuit is in operation, the source voltage is kept as constant, the SRAM operates normally, and the performance of the SRAM is not adversely affected. When the circuit is at a stand-by status, by reducing the source voltage, the sub-threshold leakage current, the gate leakage current and the junction leakage current can be affectively reduced. However, when such a structure is used, the noise margin is easily reduced; and the stability of the data stored in the SRAM is affected. On the other hand, reducing the source voltage requires an external circuit. Thus, the area of the IC chip cannot be further reduced. Further, when the source voltage is switched between two statuses, it requires extra time and extra dynamic power-consumption.
In the most circumstances, it needs to connect the double-source voltage structure in the external regions of the SRAM to generate the retention voltage to reduce the power consumption of the IC chip. However, such a circuit design is unable to effectively reduce the area of the IC chip. On the other hand, when the double-source voltage structure is performing voltage switches, it needs extra time and extra dynamic power consumption; and the SRAM is unable to effectively achieve a low-power consumption operation status.
The disclosed circuits and electronic apparatus are directed to solve one or more problems set forth above and other problems in the art.